Electronic device for data storage and a method of producing an electronic device for data storage

ABSTRACT

An electronic device for data storage and a method of producing an electronic device for data storage includes a memory storage element arranged to represent two or more memory states of the electronic device; wherein the memory storage element includes a plurality of metal nanoparticles.

TECHNICAL FIELD

The present invention relates to an electronic device for data storageand a method of producing an electronic device for data storage andparticularly, although not exclusively, to a method for producing anelectronic memory device with a layer of metal nanoparticles implementedas the memory storage element of the memory device.

BACKGROUND

Electronic memory device are widely used in various types of electronicdevices, including computers, mobile phones, digital cameras andrecorders, or even in household appliances with pre-set operationprogramme. A memory device may temporally or permanently store data inelectronic form in a memory storage element, and the stored data may beretrieved after a period of time.

Non-volatile memory device is a type of memory device which may retainthe data in electronic form for a long period of time even after thepower source of the memory device is cut off. Stored data may beretrieved by “reading” the memory storage element of the memory devicewhen the power is on again. For example, images captured by a digitalcamera may be stored in a flash memory device, and the images may beretrieved from the flash memory using another electronic device such asa computer with an appropriate flash memory reader.

SUMMARY

In accordance with a first aspect of the present invention, there isprovided an electronic device for data storage comprising a memorystorage element arranged to represent two or more memory states of theelectronic device; wherein the memory storage element includes aplurality of metal nanoparticles.

In an embodiment of the first aspect, the metal nanoparticles are formedas a monolayer.

In an embodiment of the first aspect, each of the metal nanoparticlescomprises a metal shell and a metal core.

In an embodiment of the first aspect, the metal shell is arranged toencapsulate the metal core.

In an embodiment of the first aspect, the metal shell comprises a firstmetal material, and the metal core comprises a second metal materialdifferent from the first metal material.

In an embodiment of the first aspect, each of the first metal materialand the second metal material includes at least one of Au, Ag, Pt, Pd,Ni and Cu.

In an embodiment of the first aspect, further comprises a semiconductorelement arranged to cooperate with the memory storage element inresponse to an operation of the electronic device.

In an embodiment of the first aspect, the memory storage element isarranged to modulate an electrical current passing through thesemiconductor element based on different states of the electronicdevice.

In an embodiment of the first aspect, the semiconductor elementcomprises a metal-oxide semiconductor.

In an embodiment of the first aspect, further comprises a firstdielectric layer sandwiched between the semiconductor element and thememory storage element.

In an embodiment of the first aspect, further comprises a seconddielectric layer sandwiched between the memory storage element and aconductor layer deposited on a substrate.

In an embodiment of the first aspect, wherein the substrate is aflexible substrate.

In an embodiment of the first aspect, the first dielectric layer and/orthe second dielectric layer comprises a metal-oxide material.

In an embodiment of the first aspect, each of the metal nanoparticlescomprises a diameter in a range of 10 nm to 20 nm.

In an embodiment of the first aspect, the electronic device is anon-volatile memory device.

In an embodiment of the first aspect, the electronic device isrewritable.

In accordance with a second aspect of the present invention, there isprovided a method of producing an electronic device for data storage,including the steps of: depositing a memory storage element on asubstrate of the electronic device; wherein the memory storage elementis arranged to represent two or more memory states of the electronicdevice; and wherein the memory storage element comprises a plurality ofmetal nanoparticles.

In an embodiment of the second aspect, each of the metal nanoparticlescomprises a metal shell and a metal core.

In an embodiment of the second aspect, further comprising the step ofproducing the metal nanoparticles including the steps of:

-   -   producing the metal cores of the nanoparticles; and    -   producing the metal shells arranged to encapsulate the metal        cores of the nanoparticles.

In an embodiment of the second aspect, the step of depositing a memorystorage element on a substrate of the electronic device comprising thesteps of:

-   -   producing a monolayer of nanoparticles; and    -   transferring the monolayer of nanoparticles produced to the        substrate.

In an embodiment of the second aspect, the step of transferring themonolayer of nanoparticles produced to the substrate comprising thesteps of:

-   -   attaching the monolayer of nanoparticles produced to a PDMS        surface;    -   contacting and attaching the monolayer of nanoparticles to the        substrate; and    -   detaching the PDMS surface from the monolayer of nanoparticles        attached to the substrate.

In an embodiment of the second aspect, the step of producing a monolayerof nanoparticles comprising the steps of mixing a solution containingthe nanoparticles with water and chloroform.

In an embodiment of the second aspect, the monolayer of nanoparticles isproduced at an interface between water and chloroform.

In an embodiment of the second aspect, the step of producing a monolayerof nanoparticles comprising the step of dispersing a solution containingthe nanoparticles on a water surface.

In an embodiment of the second aspect, the monolayer of nanoparticles isproduced at the water surface after a complete evaporation of a solventof the solution containing the nanoparticles.

In an embodiment of the second aspect, the substrate comprises a firstdielectric layer on a first conductive layer, and the memory storageelement is deposited on the first dielectric layer on the substrate.

In an embodiment of the second aspect, further comprising the step ofdepositing a second dielectric layer on the memory storage element.

In an embodiment of the second aspect, further comprising the step ofdepositing a semiconductor layer on the second dielectric layer.

In an embodiment of the second aspect, further comprising the step ofdepositing a second conductive layer on the semiconductor layer, whereinthe first conductive layer and the second conductive layer are arrangedto form a plurality of electrical electrodes of the electronic device.

In an embodiment of the second aspect, wherein the substrate is aflexible substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The patent or application file contains at least one drawing executed incolor. Copies of this patent or patent application publication withcolor drawing(s) will be provided by the Office upon request and paymentof the necessary fee.

Embodiments of the present invention will now be described, by way ofexample, with reference to the accompanying drawings in which:

FIG. 1 is an illustration of the electronic device for data storage inaccordance with an embodiment of the present invention;

FIG. 2 is a process flow diagram of transferring of a monolayer ofnanoparticles and the deposition of nanoparticles on a substrate inaccordance with an embodiment of the present invention;

FIG. 3 is a transmission electron microscopy (TEM) image of the memorystorage element of FIG. 1, the memory storage element is a monolayer ofa plurality of Au core-Ag shell nanoparticles;

FIG. 4 is a TEM image of the memory storage element of FIG. 1, thememory storage element is a monolayer of a plurality of Au core-Pd shellnanoparticles;

FIG. 5 is a TEM image of the memory storage element of FIG. 1, thememory storage element is a monolayer of a plurality of Au core-Pt shellnanoparticles;

FIG. 6 is a TEM image of the memory storage element of FIG. 1, thememory storage element is a monolayer of a plurality of Ag core-Au shellnanoparticles;

FIG. 7 is a plot showing a current-voltage characteristic of theelectronic device for data storage of FIG. 1 operating in six differentmemory states;

FIG. 8 is a plot showing the date retention property of the electronicdevice for data storage of FIG. 1; and

FIG. 9 is a plot showing the program-erase (P/E) endurance property ofthe electronic device for data storage of FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The inventors have, through their own research, trials and experiments,devised that, multi-bit (multi-level or multiple data-level) flashmemory based on solution-processed printing technology is important fortechnology application. Conventional flash floating gate memories inwhich only two bit data storage can be achieved are mainly based onsilicon technology and have technical hurdles in transferring toflexible substrates. In this invention, uniform monolayer of metalcore-shell nanoparticle array with ultra-high density may be utilized ascharge trapping layer for the application in flash memory.

The solution processed core-shell metal nanoparticles are used as ink tobe fabricated as large-area closely packed 2D array on the flexiblesubstrate at low temperature. Compared with conventional technology,multi-bit data storage and larger memory window is obtained due to theenhanced trapping site and almost no lateral leakage.

Referring to FIG. 1, there is provided an embodiment of an electronicdevice 100 for data storage comprising a memory storage element 102arranged to represent two or more memory states of the electronic device100; wherein the memory storage element 102 includes a plurality ofmetal nanoparticles 104.

In this embodiment, the electronic device 100 may be considered as atransistor with a floating gate form by a layer of conductive material.In such floating gate transistor structure, the floating gate 106 isseparated from the semiconductor material 108 by three layers ofmaterial, which includes two barrier layers (110, 112) and a chargetrapping layer 102. Another electrical conductive layer 114 is depositedon the other side of the semiconductor layer 108 and is furtherpatterned to form the source and drain terminals 116 of the floatinggate transistor 100. The whole device may be fabricated on a substrate118.

In an example embodiment, the electronic device 100 is fabricatedstarting with a substrate 118. The substrate 118 is preferably aflexible substrate such as Polyethylene terephthalate (PET) substrate.The PET substrate may be pre-deposited with a layer of conductivematerial 106 such as indium doped tin-oxide (ITO), or alternatively, thelayer of conductive material 106 or conductive metal-oxide may bedeposited on a bare substrate 118. The gate material 106 may bedeposited to substrates 118 by methods such as thermal evaporation, spincoating, printing, chemical vapour deposition, sputtering, pulsed laserdeposition, or any other deposition method as known by a person skilledin the art.

This conductive layer of material 106 is then patterned to form the gateof the floating-gate transistor 100. The patterning may be achieved byselective chemical etching of a conformal conductive layer 106 usingphotolithography, or the pattern is formed directly during thedeposition process using methods such as imprinting, reverse-imprinting,screen printing, physical/chemical vapour deposition with shadow masks,etc. Alternatively, this conductive layer of gate material 106 maycontain no patterns in some embodiments.

Alternatively, the substrate 118 may be selected from other types offlexible material such as polyethylene naphthalate (PEN) or polyimides(PI), or the substrate may be a rigid substrate such as silicon or glasswafers.

The barrier layers (110, 112) are electrically non-conductive so as toblock electrical current from passing through the barrier layers (110,112) directly. Preferably, the barrier layers (110, 112) may bedielectric layers, which may comprises a metal-oxide material, such asbut not limited to Al₂O₃, SiO₂, HfO₂, ZrO₂, or any other dielectricmaterial which may be suitable for blocking electrical current frompassing through, such as polymer dielectric, composite dielectric,self-assembly monolayer dielectric etc.

Preferably, a first layer of Al₂O₃ (a first dielectric layer) 110 isdeposited on the gate electrode 106 using atomic layer deposition (ALD)method, and this first layer of Al₂O₃ 110 forms the “gate oxide” of thefloating gate transistor 100. Alternatively, a dielectric layer materialdifferent from Al₂O₂ may be deposited to form the “gate oxide” 110 ofthe transistor 100, and alternative methods such as spin coating,printing, sputtering, pulsed laser deposition, physical/chemical vapourdeposition may be used for the deposition of the dielectric layer 110.

The memory storage element 102 of the electronic device 100 for datastorage is arranged to represent two or more memory states (or logicstates) of the electronic device 100. For example, in binary logic, amemory device may represent logic states of “0” or “1” (two states) in a1-bit binary logic environment. A memory device may also be arranged torepresent more than two memory states, such as logic states of “00”,“01”, “10” or “11” (four states) in a 2-bit binary logic environment.Such memory device is capable of representing three or more memorystates may be called a multi-level memory device.

In this embodiment, the memory storage element 102 includes a pluralityof metal nanoparticles 104. The term “nanoparticle (NP)”, for example,refers to a particle or an object with a diameter or size in the rangeof 1 nm to 100 nm. Nanoparticles may also be referred as ultrafineparticles. For example, an Au nanoparticle may comprise a plurality ofAu atoms, and such Au nanoparticle is physically and chemically stableto exist and has a size in the range of 1 nm to 100 nm.

Preferably, the metal nanoparticles 104 are formed as a monolayer, andare deposited on the gate oxide layer 106. Each of the metalnanoparticles 104 comprises a diameter in a range of 10 nm to 20 nm soas to avoid the quantum size effects that become pronounced innanoparticles below 5 nm, and effectively the charge trapping layer 102formed by these metal nanoparticles 104 is about 10 nm to 20 nm thick.The memory storage element or the charge trapping layer 102 comprises aplurality of charge trapping sites arrange to trap charged particles,preferably electrons, such that the memory storage element 102 isnegatively charged when electrons are trapped in the charge trappingsites. The operation of charging/discharging the charge trapping layer102 and the interaction of the charge trapping layer 102 and thefloating gate 106 transistor will be described in detail in the laterpart of the disclosure.

In this embodiment, each of the metal nanoparticles 104 composes of twodifferent metal materials, and forms a metal shell and a metal core. Themetal shell is arranged to encapsulate the metal core, and form a metalcore-metal shell nanoparticle 104. Preferably, the two different metalmaterials include at least one of Au, Ag, Pt, Pd, Ni and Cu. Forexample, the core-shell nanoparticles 104 may include (but not limitedto) Pd core-Au shell, Pd core-Ag shell, Pd core-Pt shell, Pt core-Aushell, Pt core-Ag shell, Pt core-Pd shell, Au core-Ag shell, Au core-Pdshell, Au core-Pt shell, Ag core-Pd shell, Ag core-Pt shell, Ag core-Aushell, etc.

Preferably, the nanoparticles 104 may be fabricated using solutionmethod, which includes producing the metal cores of the nanoparticles104, and producing the metal shells arranged to encapsulate the metalcores of the NPs 104. In an example embodiment of the fabrication of Aucore-Ag shell NPs 104, 50 ml of 1 mM HAuCl₄.3H₂O solution was brought tothe boil, and then 5 ml of 37.8 mM sodium citrate was added to theboiling solution. Boiling was continued for another 20 minutes togenerate the Au NPs. Au NPs were dispersed in 1 mM TRIS buffer (pH 8.5)under stirring, which contains AgNO3 solution (1.5 mM) and poly-dopamine(PDA, 1 mg/ml). The reaction was maintained under stirring for 8 hoursto generate the Au core-Ag shell NPs 104.

In another example embodiment of the fabrication of Au core-Pd shell NPs104, 50 ml of 1 mM HAuCl₄.3H₂O solution was brought to the boil, andthen 5 ml of 37.8 mM sodium citrate was added to the boiling solution.Boiling was continued for another 20 minutes to generate the Au NPs. AuNPs were dispersed in 1 mM TRIS buffer (pH 8.5) under stirring, whichcontains PdCl₂ solution (1.5 mM) and poly-dopamine (PDA, 1 mg/ml). Thereaction was maintained under stirring for 8 hours to form the Aucore-Pd shell NPs 104.

Yet in another example embodiment of the fabrication of Au core-Pt shellNPs 104, 50 ml of 1 mM HAuCl₄.3H₂O solution was brought to the boil, andthen 5 ml of 37.8 mM sodium citrate was added to the boiling solution.Boiling was continued for another 20 minutes to generate Au NPs. Au NPswere dispersed in 1 mM TRIS buffer (pH 8.5) under stirring, whichcontains H₂PtCl₆ solution (1.5 mM) and poly-dopamine (PDA, 1 mg/ml). Thereaction was maintained under stirring for 8 hours to generate the Aucore-Pt shell NPs 104.

Yet in another example embodiment of the fabrication of Ag core-Au shellNPs 104, 50 ml of 1 mM aqueous Ag (I) salt solution was mixed with 50 mlof ethanol containing 1 ml of DDA. After 2 minutes of stirring, 50 ml oftoluene was added, and stirring is kept for 1 minute. Phase transfer ofmetal ions from water to toluene would then be completed. Transfer of Au(III) salt from water to toluene was followed in the same way. At 100°C., 1 ml of 100 mM of toluene solution of HDD was added to 20 ml of thetoluene solution of Ag (I) salt, and the mixture was agitated forseveral minutes. 5 ml of Ag seed organosol (from step 2 ) in toluenewere heated at 80° C. for 5 min, followed by the addition of 5 ml oftoluene solution of Au (III) salt. Heating at 80° C. continued foranother 20 min under magnetic stirring to generate the Ag core-Au shellNPs 104.

After the production of the metal core-shell NPs 104, the NPs 104 may bedeposited on the gate dielectric layer 110 as a monolayer of such metalcore-shell NPs 104, which include the steps of producing a monolayer ofNPs 104 and then transferring the monolayer of NPs 104 to the gate oxidelayer 110 on the substrate 118. In an example embodiment of theproduction of a monolayer of NPs 104, 40 μl of metal core-shell NPs 104(produced in the as abovementioned) is added into 960 μl H₂O. Then, 0.5ml chloroform was added to the mixture. With the assistance of gentleshaking for better mixing, a thin layer (monolayer) of NPs 104 wasformed at the interface of two solution phases.

In another example embodiment of the production of a monolayer of NPs104, after the fabrication of Ag core-Au shell NPs 104, theNP-containing toluene/hexane (1:1) solution is dispersed on watersurface until complete evaporation of the solvent. After that, amonolayer of Ag core-Au shell NPs 104 is formed on the water surface.

With reference to FIG. 2, the monolayer of NPs 104 may be deposited tothe substrate using micro-contact printing. In this example, themonolayer of NPs 104 is lifted from the water surface 202 by attachingthe monolayer of nanoparticles 104 produced to a PDMS surface 204,contacting and attaching the monolayer of nanoparticles 104 to thesubstrate 206, and then detaching the PDMS surface 204 from themonolayer of nanoparticles 104 attached to the substrate 206.Preferably, a flat PDMS pad 206 may be used for lifting the monolayer ofNPs 104 from the water surface 202 or the water/chloroform interface andthen brought into conformal contact with the substrate 206 for about apredetermined period of time, such as 10 seconds. The TEM images ofmonolayers of Au core-Ag shell NPs, Au core-Pd shell NPs, Au core-Ptshell NPs and Ag core-Au shell NPs are shown in FIGS. 3 to 6respectively.

Alternatively, the charge trapping layer 102 or the metal nanoparticles104 may be deposited to the gate dielectric layer 110 on the substrate118 by other methods such as spin coating or thermal evaporation, or anyother deposition methods as known by a person skilled in the art.

Referring back to FIG. 1, on top of the charge trapping layer 102 or thememory storage element 102, a second dielectric layer 112, preferably alayer of material which is the same as the first dielectric layer 110 ofthe gate oxide layer underneath the charge trapping layer 102, such asAl₂O₃, may be deposited on the charge trapping layer 102. In thisstructure, the charge trapping layer 102 is sandwiched between twodielectric layers (110, 112). The second dielectric layer may beconsidered as a tunnel oxide layer 112 in a floating gate transistor100, which allows charges to tunnel through between the semiconductormaterial 108 and the charge trapping layer 102, but blocks directelectrical current passing through. Alternatively, the second dielectriclayer 112 may be formed with a dielectric material or electricallynon-conductive material different from the first dielectric layer 110.Similarly, the second dielectric layer 112 may be deposited by usingALD, or by another suitable method for depositing a dielectric layer aspreviously mentioned in the disclosure.

After the deposition of the second dielectric layer 112, a layer ofsemiconductor 108, preferably ZnO, may be deposited on the dielectriclayer 112 on the substrate 118. The semiconductor layer 108 serves asthe active layer in the electronic device 100. This semiconductorelement 108 is arranged to cooperate with the memory storage element 102in response to an operation of the electronic device 100. The layer ofZnO may be deposited using a solution process, such as spin coating.Alternatively, other semiconductor material (such as but not limited toorganic semiconductor, inorganic semiconductors, or compositesemiconductors) may be applied by using various suitable methods,including spin coating, printing, thermal evaporation, physical/chemicalvapour deposition, sputtering, pulsed laser deposition, etc.

To complete the floating gate transistor structure, a layer ofconductive material 114 is deposited on the semiconductor layer 108 toform the source/drain terminals 116 of the electronic device 100. Inthis embodiment, a layer of ITO 114 is deposited on ZnO semiconductorlayer 108, which may be further patterned by selective chemical etchingusing photolithography method (or other patterning method as previouslymentioned in the disclosure). Alternatively, other materials withappropriate work functions, which may form a desire ohmic contact,near-ohmic contact or tunnelling-ohmic contact with a correspondingsemiconductor material deposited as active layer, such as conductivemetal-oxide, conductive polymer, metal or graphene, may be used as thesource/drain terminal 116 of the electronic device 100.

Optionally, a plurality of electronic device 100 may be integrated toform a memory device with a larger memory size. Additionally, othertypes of electronic devices such as controllers and antennas may beintegrated or connected to the memory device 100 to provide additionalfunctions. Alternatively, one or more electronic devices 100 may beintegrated to other electronic devices or integrated circuits to providememory functions to these electronic devices or integrated circuits.

In one example embodiment, the size of metal core-shell nanoparticles104 around 10 nm to 20 nm to avoid the quantum size effects that becomepronounced in nanoparticles 104 below 5 nm. One particular type ofcore-shell nanoparticles 104, selected from Pd core-Au shell, Pd core-Agshell, Pd core-Pt shell, Pt core-Au shell, Pt core-Ag shell, Pt core-Pdshell, Au core-Ag shell, Au core-Pd shell, Au core-Pt shell, Ag core-Pdshell, Ag core-Pt shell and Ag core-Au shell, forms the memory storageelement 102. The flexible substrate 118 deposited with Al₂O₃ layer 110was washed, preferably by acetone, ethanol and deionized water. Thefabrication method of 2D core-shell nanoparticle super lattices is bycontrolling the evaporation of nanoparticles 104 dispersed in a binarysolvent mixture on the deionized water surface. The core-shellnanoparticle self-assembled monolayer were obtained by spreadingnanoparticle solution onto the surface of the concave deionized water,the Langmuir film was then lifted from the water surface using a flatPDMS pad and then this pad is brought into conformal contact with thesubstrate for about 10 seconds. Memory devices 100 were fabricated onflexible film 118 with 100 nm indium tin oxide (ITO) 106 as gateelectrode. Al₂O₃ layers (110, 112) were deposited using a Savannah 100ALD system at a substrate temperature of 80° C. Solution processed metaloxide semiconductor (such as ZnO) 108 was used as the active layer inthe memory structure 100. ITO layer 114 was used as the source and drainelectrodes 116.

Each of the layers of the electronic device 100 as shown in FIG. 1 maybe in a range of preferable thickness. For example, the thickness of thegate electrode 106 may be about 20 nm to 40 nm, the thickness of thedielectric layers (110, 112) may be about 20 nm to 50 nm, the thicknessof the semiconductor layer 108 may be about 10 nm to 40 nm, thethickness of the charge trapping layer 102 may be about 10 nm to 20 nm,and the thickness of the source/drain layer 114 may be about 20 nm to 50nm. Alternatively, to optimize the electronic device 100 based ondifferent fabrication processing method or the desired operation of theelectronic device 100, other suitable thickness of each of theindividual layers may be applied.

Advantageously, long retention time and good endurance property can beachieved in the electronic device for data storage. The printable metalcore-shell nanoparticle monolayer through micro-contact printingtechnique has great potential for scaling down the current state-of-artflash memory devices. The key device elements (core-shell nanoparticles)are fabricated via low temperature processes, which can be readilyadopted on plastic substrates. The dielectric layer as well as thesemiconductor layer can also be fabricated at low temperature which isextendable for low-cost large area fabrication of flexible flashmemories. In addition, since plastic substrate may provide excellentmechanical stiffness, the memory devices supported by the flexiblesubstrate is also provided with excellent mechanical property, and henceenhancing the data retention time and endurance property.

Such embodiments are also advantages in that, the electronic device fordata storage is suitable for fabricating on various kind of substrateincluding flexible substrates. This allows the memory device to bedeposited, mounted, or even directly printed on substrates such as RFIDtags, flight tickets, portable electronic devices or even speciallydesigned electronic apparatus with curved surfaces. In addition, theseembodiments may operate in low voltage which is more suitable forapplications such as passive tags. Lower programming voltage may alsorequire simpler driving controllers.

Additionally, the electronic device for data storage may be fabricatedwith low temperature processes and minimized steps involving vacuumprocesses. In some preferred embodiments, the fabrication processesmostly involve solution processes, and the deposition of the key element(the charge trapping layer) involve micro-contact printing. Unlikesilicon device fabrication which highly depends on high vacuum and hightemperature processes, the processing window is much wider which lead topossibly higher yield. Low temperature processes also allow the use of amuch wider range of substrates, including flexible plastic or papersubstrates.

With reference to FIG. 7, there is shown a current-voltagecharacteristic of the electronic device 100 for data storage inaccordance with an embodiment of the present invention. In thisembodiment, the electronic device 100 is arranged to represent six datalevels or memory states.

In a programming or writing operation, a positive voltage bias isapplied between the gate and the source terminals, to drive electronstunnelling through the tunnel oxide and the electrons are trapped in thecharge trapping layer 102. Higher the voltage bias applied between thegate and the source, more electrons are trapped in the charge trappinglayer 102. In the embodiment as shown in FIG. 7, six different positivevoltage bias is applied between the gate and the source terminals torecord six different memory states. For example, to programme the memorydevice 100, a gate-source bias of 6 V may be applied for 1 second torecord a memory state representing data level 1, 5 V may be applied for1 second to record a memory state representing data level 2, 4 V may beapplied for 1 second to record a memory state representing data level 3,3 V may be applied for 1 second to record a memory state representingdata level 4, 2 V may be applied for 1 second to record a memory staterepresenting data level 5, and the uncharged memory device may representa memory state of data level 6 respectively. Alternatively, based ondifferent writing and/or reading methodology or algorithm, gate biasand/or bias duration may be applied to programme the memory device 100to a memory state representing a predetermined data level.

In the read operation, positive voltage bias (2V) is applied between thegate and the source terminal, positive voltage bias (3V) is appliedbetween the drain and the source terminal. The operation is based on theI-V curve at V_(GS)=2 V. Since the memory device 100 is previouslyprogrammed by injecting negatively charged electrons in the chargetrapping layer 102 underneath the gate electrode 106, the appliedpositive gate bias is partially compensated by the negatively chargedcharge trapping layer, and hence the “effective gate bias” is lower thanthe applied gate bias, and the difference is dependent on the amount ofcharges trapped in the charge trapping layer, and hence the memorystorage element is arranged to modulate an electrical current passingthrough the semiconductor element 108 based on different states of theelectronic device. In such reading operation, the six data level is readas: Data level 1 (1.6E-11 A), Data level 2 (1.1E-10 A), Data level 3(7.7E-10 A), Data level 4 (5.6E-9 A), Data level 5 (2.5E-8 A), Datalevel 1 (4.6E-8 A). Alternatively, other read algorithm, such as readingby applying different V_(GS) and/or V_(DS) may be applied, and thememory device may represent a number of data levels different from six,based on different writing and reading operation.

In the erase operation, sufficient negative voltage bias is appliedbetween the gate and the source terminal (such as a gate-source bias of−6 V for 1 second), electrons are released from the charge trappinglayer 102 to the semiconductor layer 108. As a result, the memory device100 is reverted back to the uncharged states and is rewritable orreprogrammable. Alternatively, based on different writing and/or erasingmethodology or algorithm, gate bias and/or bias duration may be appliedto erase the memory device 100 to a state ready for reprogramming.

With reference to FIG. 8, there is shown the data retention property ofthe electronic device 100 for data storage. In this test, the electronicdevice 100 is written with data level 1 and data level 6 and the deviceis read at 10, 100, 1000, 10000, 100000 and 1000000 seconds respectivelyafter programming. The data plot is extrapolated to about 3×10⁹ seconds,which represent a period of 10 years after programming. The results showthat the difference between estimated currents representing twodifferent data levels are sufficiently large enough (more than 2 ordersof magnitude) which suggests that the data retention property of themulti-level memory device is excellent, and the electronic device 100 isa non-volatile memory device.

With reference to FIG. 9, there is shown the program-erase (P/E)endurance property of the electronic device 100 for data storage. Inthis test, read operations are carried out after certain program/erasecycling test (1, 10, 100, 1000, 10000, 100000, 1000000), in which onecycling test is defined as first programming the electronic device 100at a positive gate bias then erase at a negative gate bias. The resultsshow that after 1000000 P/E cycles, the difference between the twomeasured currents representing two different data levels (level 1 andlevel 6) are sufficiently large (more than 2 orders of magnitude), whichsuggests that the P/E endurance property of the multi-level memorydevice is excellent, and the electronic device 100 is rewritable.

Without deviating from the spirit of the invention, the electronicdevice for data storage may be modified to include other transistorstructures. In some embodiments, the memory device can be arranged tooperate as non-rewritable storage, temporary storage, or any other usageas known by a person skilled in the art.

It will be appreciated by persons skilled in the art that numerousvariations and/or modifications may be made to the invention as shown inthe specific embodiments without departing from the spirit or scope ofthe invention as broadly described. The present embodiments are,therefore, to be considered in all respects as illustrative and notrestrictive.

Any reference to prior art contained herein is not to be taken as anadmission that the information is common general knowledge, unlessotherwise indicated.

The invention claimed is:
 1. A method of producing an electronic devicefor data storage comprising the steps of: producing a plurality of metalnanoparticles, wherein the plurality of metal nanoparticles each includea metal core and a metal shell, said step of producing a plurality ofmetal nanoparticles including the steps of: producing the metal cores ofthe metal nanoparticles; and producing the metal shells arranged toencapsulate the metal cores of the metal nanoparticles; and depositing amemory storage element on a substrate of the electronic device; whereinthe memory storage element includes the plurality of metalnanoparticles; wherein the memory storage element is arranged torepresent two or more memory states of the electronic device; andwherein the step of depositing the memory storage element on thesubstrate of the electronic device comprises the steps of: producing amonolayer of the plurality of metal nanoparticles; and thereaftertransferring the produced monolayer the substrate.
 2. A method ofproducing an electronic device for data storage in accordance with claim1, wherein the step of transferring the monolayer of nanoparticlesproduced to the substrate comprising the steps of: attaching themonolayer of nanoparticles produced to a PDMS surface; contacting andattaching the monolayer of nanoparticles to the substrate; and detachingthe PDMS surface from the monolayer of nanoparticles attached to thesubstrate.
 3. A method of producing an electronic device for datastorage in accordance with claim 1, wherein the step of producing amonolayer of nanoparticles comprising the step of mixing a solutioncontaining the nanoparticles with water and chloroform.
 4. A method ofproducing an electronic device for data storage in accordance with claim3, wherein the monolayer of nanoparticles is produced at an interfacebetween water and chloroform.
 5. A method of producing an electronicdevice for data storage in accordance with claim 1, wherein the step ofproducing a monolayer of nanoparticles comprising the step of dispersinga solution containing the nanoparticles on a water surface.
 6. A methodof producing an electronic device for data storage in accordance withclaim 5, wherein the monolayer of nanoparticles is produced at the watersurface after a complete evaporation of a solvent of the solutioncontaining the nanoparticles.
 7. A method of producing an electronicdevice for data storage in accordance with claim 1, wherein thesubstrate is flexible.
 8. A method of producing an electronic device fordata storage comprising the steps of: producing a plurality of metalnanoparticles; depositing a memory storage element on a substrate of theelectronic device, wherein the memory storage element is arranged torepresent two or more memory states of the electronic device, whereinthe memory storage element includes the plurality of metalnanoparticles, wherein the substrate comprises a first dielectric layeron a first conductive layer, and the memory storage element is depositedon the first dielectric layer on the substrate; depositing a seconddielectric layer on the memory storage element; depositing asemiconductor layer on the second dielectric layer; and depositing asecond conductive layer on the semiconductor layer, wherein the firstconductive layer and the second conductive layer are arranged to form aplurality of electrical electrodes of the electronic device.
 9. A methodof producing an electronic device for data storage in accordance withclaim 8, wherein the substrate is flexible.